An efficient implementation method of parallel processing Viterbi decoders for UWB systems

In this paper, we present an efficient implementation method for parallel processing Viterbi decoders in UWB systems. In our method, we use an automatic HDL code generator designed by high level languages (C or C++) to produce the synthesizable HDL code for a parallel processing Viterbi decoder automatically depending on the hardware architecture for parallel processing as well as parameters for channel coding, which makes it easy to find the optimum architecture under the specified working speed and CMOS technology. We apply the proposed method to the design of Viterbi decoders for UWB systems, in which it is an important issue to find the optimum architecture working at the speed of 132 MHz in 4-way parallel processing. From the results, we can find that our scheme can produce all the possible architectures of Viterbi decoder properly without manual efforts and that the Viterbi decoder with radix-4² ACS structure has the lowest hardware costs working at the required clock speed under 0.13 um CMOS technology.