Achieving sub-adiabatic energy dissipation by varying VBS

This paper proposes a new method of reducing the energy dissipation below that of quasi-adiabatic circuit. Adiabatic logic style is proving to be an attractive solution for low power digital design. Many researchers have introduced different adiabatic logic styles in last few years and proved that these are better than CMOS as far as power dissipation is concerned. In this paper, we present control circuits for sub-adiabatic energy dissipation and show that the energy dissipation of the quasi-adiabatic circuit can be further reduced if we control bulk-to-source voltage, V_BS appropriately. All the inverter circuits are designed using 180 nm technology in Cadence design environment.