• DocumentCode
    495877
  • Title

    A middleware aided robust and fault tolerant dynamic reconfigurable architecture

  • Author

    Dadji, Yannick ; Osterloh, Björn ; Michalik, Harald

  • Author_Institution
    Inst. of Comput. & Commun. Network Eng., Tech. Univ. Braunschweig, Braunschweig, Germany
  • fYear
    2009
  • fDate
    22-24 June 2009
  • Firstpage
    572
  • Lastpage
    579
  • Abstract
    Dynamic reconfiguration enhances embedded system with at run-time adaptive functionality and is an improvement in terms of resource utilization and system adaptability. SRAM-based FPGAs provides a dynamic reconfigurable platform with high logic density. The requirements for such an embedded high flexible system based on FPGAs are robustness and reliability to prevent operation interrupts or even system failures. The complexity of a dynamic reconfigurable system with adaptive processing module demands high effort for the user. Therefore a high level abstraction of the communication issues is required to support application development by an appropriate middleware. To achieve such a flexible embedded system we present our network-on-chip (NoC) approach system-on-chip wire (SoCWire) and outline its performance and suitability for robust dynamic reconfigurable systems. Furthermore we introduce a suitable embedded middleware concept to support the system reconfiguration and the software application development process.
  • Keywords
    SRAM chips; fault tolerant computing; field programmable gate arrays; middleware; network-on-chip; reconfigurable architectures; system-on-chip; FPGA; NoC; SRAM; SoCWire; adaptive processing module; dynamic reconfiguration; fault tolerant dynamic reconfigurable architecture; flexible embedded system; middleware; network-on-chip; software application development process; system-on-chip wire; Application software; Embedded system; Fault tolerance; Field programmable gate arrays; Middleware; Network-on-a-chip; Reconfigurable architectures; Reconfigurable logic; Resource management; Robustness; FPGA; Middleware; Network-on-Chip; SoCWire; Virtex;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reconfigurable Mechanisms and Robots, 2009. ReMAR 2009. ASME/IFToMM International Conference on
  • Conference_Location
    London
  • Print_ISBN
    978-88-89007-37-2
  • Electronic_ISBN
    978-1-876346-58-4
  • Type

    conf

  • Filename
    5173886