An all digital DSSS satellite navigation & position transceiver design and VLSI implementation

The considerations of hardware implementation on an all digital direct-sequence spread spectrum (DSSS) satellite navigation & position transceiver is discussed, including function partition, parameter determination and architecture optimizing. The characteristic of this transceiver lies in directly sampling to the A/D intermediate frequency signal after down-conversion. The digital signal after sampling is dealt with the baseband processing consisting of FPGA and DSP. To achieve the balance between fast acquisition and minimum hardware consumption, the transceiver employs a sliding correlator acquisition strategy and adaptive detection threshold, and the resultant correlator complexity is reduced by structure optimization. The overall architecture is very suitable for VLSI implementation. The design has been implemented on Altera Cyclone EP1C12Q240I7 FPGA device and TI TMS320VC5416 DSP device. The project results show that this modern approach is not only rational and feasible but also abundant in dependability considerations. It can satisfy the requirements for the design index, and has certain surplus.