DocumentCode
497157
Title
20nm-node planer MONOS cell technology for multi-level NAND Flash Memory
Author
Yaegashi, T. ; Okamura, T. ; Sakamoto, W. ; Matsunaga, Y. ; Toba, T. ; Sakuma, K. ; Gomikawa, K. ; Komiya, K. ; Nagashima, H. ; Akahori, H. ; Sekine, K. ; Kai, T. ; Ozawa, Y. ; Sugi, M. ; Watanabe, S. ; Narita, K. ; Umemura, M. ; Kutsukake, H. ; Sakuma, M
Author_Institution
Center for Semicond. R&D, Toshiba Corp., Yokohama, Japan
fYear
2009
fDate
16-18 June 2009
Firstpage
190
Lastpage
191
Abstract
20 nm-node planer MONOS NAND Flash memory is developed for the first time. Excellent performances such as fast program speed are realized without using FinFET structure. Furthermore, potential of tight Vth distribution is confirmed using 50 nm-node cells. These properties indicate that planer MONOS cell technology developed in this work can be one of candidates for multi-level NAND Flash memory with 20 nm-node and beyond.
Keywords
NAND circuits; flash memories; MONOS NAND Flash memory; multilevel NAND Flash memory; planer MONOS cell technology; size 20 nm; size 50 nm; Dielectric films; Electrodes; FinFETs; Laboratories; Large scale integration; MONOS devices; Manufacturing processes; Metalworking machines; Semiconductor device manufacture; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 2009 Symposium on
Conference_Location
Honolulu, HI
Print_ISBN
978-1-4244-3308-7
Type
conf
Filename
5200594
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