Efficient pnp characteristics of pMOS transistors in sub-0.13µm ESD protection circuits

An analysis of pMOS transistors in snapback conduction mode for a sub-0.13µm technology will be presented. The pMOS n-well confined behavior vs. nMOS will be discussed. It will be shown that n-well resistance control under ESD conditions is the key factor to maintaining a sufficient ballast resistance in fully silicided technologies. The snapback and breakdown behavior will be discussed with respect to both physical mechanisms and process features. New reliability issues arising from a highly performing pMOS pull up transistor will be described. Possible solutions at the process, device and circuit level will be presented to minimize these reliability concerns.