• DocumentCode
    502696
  • Title

    New considerations for MOSFET power clamps

  • Author

    Poon, Steven S. ; Maloney, Timothy J.

  • Author_Institution
    Intel Corporation, SC12-607, 2200 Mission College Blvd., Santa Clara, CA 95052, USA
  • fYear
    2002
  • fDate
    6-10 Oct. 2002
  • Firstpage
    1
  • Lastpage
    5
  • Abstract
    Two ESD clamp circuit design techniques have been developed to reduce cell size and to combat the effects of gate leakage that have become significant in recent generations of digital CMOS process technology. Such clamps have proven to be able to withstand HBM stresses of 6kV and CDM pulses of 1.2kV.
  • Keywords
    Clamps; Electrostatic discharge; Gate leakage; Integrated circuit technology; Inverters; MOSFET circuits; Power MOSFET; Power generation; Power supplies; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    2002 Electrical Overstress/Electrostatic Discharge Symposium, 2002. EOS/ESD '02.
  • Conference_Location
    Charlotte, NC, USA
  • Print_ISBN
    978-1-5853-7040-5
  • Electronic_ISBN
    978-1-5853-7040-5
  • Type

    conf

  • Filename
    5267046
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=502696