DocumentCode
502998
Title
SoC — A real challenge for ESD protection?
Author
Gossner, H. ; Domanski, K. ; Drüen, S. ; Esmark, K. ; Pessl, P. ; Russ, C. ; Stadler, W. ; Zängl, F.
Author_Institution
COM CAL D DAT LIB ESD, Infineon Technol., Munich, Germany
fYear
2005
fDate
8-16 Sept. 2005
Firstpage
1
Lastpage
10
Abstract
We are facing the task to provide ESD protection concepts for complex system on chip (SoC) solutions including RF components, high voltage circuits and mixed signal functionality. Critical issues like protection of sensitive interfaces between supply domains, ESD master bus, system level ESD/EOS requirements and test methodology, are reviewed. Concepts are presented for a SoC and a system-in-package product in a 0.13 mum CMOS process.
Keywords
CMOS integrated circuits; electrostatic discharge; system-in-package; system-on-chip; CMOS process; EOS requirement; ESD master bus; RF component; high-voltage circuit; mixed signal functionality; size 0.13 mum; system level ESD protection; system on chip solution; system-in-package product; CMOS process; Circuit testing; Earth Observing System; Electrostatic discharge; Protection; RF signals; Radio frequency; System testing; System-on-a-chip; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Overstress/Electrostatic Discharge Symposium, 2005. EOS/ESD '05.
Conference_Location
Tucson, AZ
Print_ISBN
978-1-58537-069-6
Electronic_ISBN
978-1-58537-069-6
Type
conf
Filename
5271755
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