DocumentCode
503022
Title
Physics and design optimization of ESD diode for 0.13μm PD-SOI technology
Author
Entringer, Christophe ; Flatresse, Philippe ; Salome, Pascal ; Nouet, Pascal ; Azais, Florence
Author_Institution
ST Microelectron. Crolles, Crolles, France
fYear
2005
fDate
8-16 Sept. 2005
Firstpage
1
Lastpage
7
Abstract
This paper investigates the physics of 0.13 mum partially depleted SOI gated diodes through TLP measurements and TCAD simulations. The impact of gate length, well type, oxide thickness, gate to contact distance and presence of gate on ESD performance are evaluated and discussed. It is shown that the gate coupling effect decreases ESD performance.
Keywords
electrostatic devices; electrostatic discharge; semiconductor diodes; silicon-on-insulator; technology CAD (electronics); ESD diode; TCAD simulations; TLP measurements; contact distance; design optimization; gate length; oxide thickness; partially depleted SOI gated diodes; physics; well type; Anodes; Charge carrier processes; Design optimization; Diodes; Electrostatic discharge; Heating; Physics; Silicon; Stress; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Overstress/Electrostatic Discharge Symposium, 2005. EOS/ESD '05.
Conference_Location
Tucson, AZ
Print_ISBN
978-1-58537-069-6
Electronic_ISBN
978-1-58537-069-6
Type
conf
Filename
5271821
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