Impact of stress engineering on high-k metal gate ESD diodes in 32nm SOI technology

Author

Mitra, Souvick ; Gauthier, Robert ; Putnam, Chris S. ; Halbach, Ralph ; Seguin, Chris

Author_Institution

IBM Microelectron. Semicond. R&D Center, Essex Junction, VT, USA

fYear

2009

fDate

Aug. 30 2009-Sept. 4 2009

Firstpage

1

Lastpage

7

Abstract

Low current and high current ESD characteristics of the Poly-Bounded and High-k Metal Gate-bounded ESD diodes with varying stress components are studied in 32 nm SOI technology. It is observed that embedded SiGe (e-SiGe) stress on the anode degrades the ESD protection performance significantly mainly due to the introduction of defects in the active region. Compressive stress liners, tensile stress liners and stress due to Stress Memorization Technique (SMT) show only a marginal shift in the diode performance.

Keywords

CMOS logic circuits; CMOS memory circuits; Ge-Si alloys; SRAM chips; electrostatic discharge; field effect transistors; high-k dielectric thin films; semiconductor diodes; silicon-on-insulator; ESD protection; SOI CMOS technology; SRAM; SiGe; active region; compressive stress liners; defects; high-k metal gate-bounded ESD diodes; size 32 nm; stress memorization technique; tensile stress liners; thin-oxide NFETs; Anodes; Compressive stress; Degradation; Diodes; Electrostatic discharge; Germanium silicon alloys; High K dielectric materials; High-K gate dielectrics; Silicon germanium; Tensile stress;

fLanguage

English

Publisher

ieee

Conference_Titel

EOS/ESD Symposium, 2009 31st

Conference_Location

Anaheim, CA

Print_ISBN

978-1-58537-176-1

Electronic_ISBN

978-1-58537-176-1

Type

conf

Filename

5340138