• DocumentCode
    506173
  • Title

    The i860TM 64-bit supercomputing microprocessor

  • Author

    Kohn, Leslie ; Margulis, Neal

  • Author_Institution
    Intel Corporation, Santa Clara, CA
  • fYear
    1989
  • fDate
    12-17 Nov. 1989
  • Firstpage
    450
  • Lastpage
    456
  • Abstract
    The Intel i860TM processor is a RISC-based microprocessor incorporating a RISC core with memory management, a floating point unit, and caches on a single chip. The 1,000,000 transistors allow a single chip implementation with highly optimized interunit communication and wide internal data buses. The parallelism and pipelining between the execution units, and the innovative cache management techniques are under explicit control of software. Vectorizable applications can use the pipelined adder and multiplier units to achieve up to 80 Mflops at 40 Mhz for the inner loops of common calculations. Special instructions allow using the data cache as a flexible vector register and support high data bandwidth from main memory. Finally, to support visualization of data, special hardware for 3D graphics is included.
  • Keywords
    Application software; Bandwidth; Communication system control; Data buses; Innovation management; Memory management; Microprocessors; Pipeline processing; Reduced instruction set computing; Registers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Supercomputing, 1989. Supercomputing '89. Proceedings of the 1989 ACM/IEEE Conference on
  • Conference_Location
    Reno, NV, United States
  • Print_ISBN
    0-89791-341-8
  • Type

    conf

  • DOI
    10.1145/76263.76313
  • Filename
    5349008