Design and implementation of an ultra-high speed data acquisition system for HRRATI

Data acquisition system (DAS) is a fundamental functional part in every radar application, especially when used for high range resolution radar system. This paper presents a high speed and reliable DAS of a high range resolution radar used for acquiring traffic flow information (HRRATI). The system uses high performance field programmable gate array (FPGA) to cope with the data transformed by the high speed 8-bits analog-to-digital converter (ADC08D500), which performs digitization of the dual channels radar echo signals with sampling rate at 500 MHz. The signal bandwidth up to 180 MHz in each channel, then the system preprocesses all the data onboard in real time. In view of the broad bandwidth of the signal and high sampling rate, clock jitter, signal integrity and EMI/EMC issues assume great importance and pose a great challenge to the printed circuit board (PCB) design. This paper gives a thorough investigation of such problems. Finally, clock jitter and ENOB test experiment results show that the DAS is capable of sampling the radar signal effectively.