A 5-Gb/s Serial-Link Redriver With Adaptive Equalizer and Transmitter Swing Enhancement

A single-lane, dual-channel, 5-Gb/s serial link redriver with no clock data recovery (CDR) or phase-locked loop (PLL) has been developed by using a standard 0.13- μm CMOS technology. New features and techniques have been developed in both the architecture and the analog modules to meet the jitter and protocol requirements for a redriver for multi-Gb/s operation, which is made difficult by the lack of CDR and a PLL. These techniques include: 1) adaptive receiver equalization; 2) enhanced transmitter output swing and programmable de-emphasis/swing settings; 3) a robust state flow control combined with various signal detectors to provide automatic state and mode switching without affecting operations of upstream and downstream ports. The redriver chip consumes 165 mA in 5 Gb/s bidirectional full-duplex operation from a single 3.3 V power supply.