• DocumentCode
    507399
  • Title

    A framework for early and systematic evaluation of design rules

  • Author

    Ghaida, Rani S. ; Gupta, Puneet

  • Author_Institution
    Electr. Eng. Dept., Univ. of California, Los Angeles, CA, USA
  • fYear
    2009
  • fDate
    2-5 Nov. 2009
  • Firstpage
    615
  • Lastpage
    622
  • Abstract
    Design rules have been the primary contract between technology and design and are likely to remain so to preserve abstractions and productivity. While current approaches for defining design rules are largely unsystematic and empirical in nature, this paper offers a novel framework for early and systematic evaluation of design rules and layout styles in terms of major layout characteristics of area, manufacturability, and variability. Due to the focus on co-exploration in early stages of technology development, we use first order models of variability and manufacturability (instead of relying on accurate simulation) and layout topology/congestion-based area estimates (instead of explicit and slow layout generation). The framework is used to efficiently co-evaluate several debatable rules (evaluation for a 104-cell library takes 20 minutes). Results show that: a) diffusion-rounding mainly from diffusion power-straps is a dominant source of variability, b) cell-area overhead of fixed gate-pitch implementation compared to 1D-poly implementation is tolerable (5%) given the improvement in variability, and c) 1D-poly restriction, which improves manufacturability and variability, has almost no area overhead compared to 2D-poly. In addition, we explore gate-spacing rules using our evaluation framework. This exploration yields almost identical values as those of a commercial 65 nm process, which serves as a validation for our approach.
  • Keywords
    integrated circuit layout; integrated circuit manufacture; cell area overhead; debatable rule; design rule evaluation; diffusion rounding; gate spacing rule; layout styles; size 65 nm; Circuits; Contracts; Design methodology; Libraries; Lithography; Permission; Productivity; Pulp manufacturing; Topology; Virtual manufacturing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design - Digest of Technical Papers, 2009. ICCAD 2009. IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA
  • ISSN
    1092-3152
  • Print_ISBN
    978-1-60558-800-1
  • Electronic_ISBN
    1092-3152
  • Type

    conf

  • Filename
    5361232