Scalable arbitration of partitioned bus interconnection networks in 3D-IC systems

In this paper, we describe a scalable interconnection network architecture intended for very large multicore processors implemented on stacked chip 3D integrated circuits (3D-IC). These networks provide fully interconnected, low latency, single hop performance with wiring complexity that scales linearly with the size of the network. The enabling technology for these networks is a novel, fully distributed arbitration and control algorithm that operates solely at the edges of the network without the need for any routers within the network core. This paper is focused on a description of that algorithm. We present simulation results for average, worst-case, and per-node latencies showing that our arbitration algorithm performs efficiently, scales for a wide range of partition sizes, and effectively manages highly non-uniform traffic patterns.