A novel gated scan-cell scheme for low Capture Power (LCP) in at-speed testing

In recent years, power dissipation is a large challenge for IC design. Furthermore, the capacitance excessive transition may lead to circuit reliable reduction and heat problem. In this paper, we proposed a new algorithm to reduce the transition count of scan cell during capture operation. The clock gating technique, fault diagnosis, and fault dropping are used to decrease the capture power dissipation. The control logic is required in our architecture, and we considered the complexity of circuit, simultaneously. Experimental results for ISCAS´89 benchmark circuits show that the proposed technique effectively reduces the average capture power by 39.81% and the area of decoding logic is approximately 6%.