Evaluation of the state-of-the art statistical leakage estimation methods using the BSIM4 transistor model

Due to the continued scaling down of the semiconductor process technology, the necessity for variation aware leakage estimation is being emphasized today. Several statistical leakage estimation (SLE) methods have been proposed to deal with the process variation. The state-of-the art SLE methods show pretty accurate results when the BSIM3 transistor model is used. However, because the variation of leakage current has a non lognormal distribution in the recent transistor model BSIM4, the state-of-the art SLE methods are losing their effectiveness. In this paper, we verify the accuracy of the state-of-the art SLE methods using the BSIM4 model, and compare those results to the results obtained by using the BSIM3 model. In the experiments using ISCAS-85 benchmark circuits, the results obtained by using the BSIM4 model showed an average leakage mean and standard deviation errors of 18% and 19%, respectively. On the other hand, the results obtained by using the BSIM3 model showed more accurate results that average leakage mean and standard deviation errors of 2.17% and 4.8%, respectively.