Heuristic techniques for automatic synthesis of clock mesh

This paper presents a set of heuristics for automatic clock mesh synthesis, including mesh planning, placement of stems and routing of flip-flops (FFs). Firstly, a fast and accurate method is introduced for determining the number of mesh stems. Secondly, a balancing placement and routing (BPR) method is presented for adjusting the spacing between stems and balancing the load to each stem. Experimental results show that the proposed heuristics can achieve skew reduction for about 44.3% on average at the expense of only 1.7% increase in total wirelength and 0.2% increase in power, compared to the uniform placement and route (UPR) method reported in the literature.