A multi Gbps 10-PAM receiver in 0.18μm CMOS technology

Author

Lee, Jeongjun ; Jeong, Jikyung ; Burm, Jinwook

Author_Institution

Dept. of Electron. Eng., Sogang Univ., Seoul, South Korea

fYear

2009

fDate

14-16 Dec. 2009

Firstpage

89

Lastpage

92

Abstract

We report a receiver for ten-level pulse-amplitude modulated (10-PAM) encoded data signals, which was measured to receive data at 8 Gb/s at a maximum frequency (2 GHz). To increase data bit-rate and reduce BER, we designed this circuit by using a current mode amplifier, high speed comparator and a current-mode logic (CML) circuit. The 10-PAM receiver is designed in 0.18 Â¿m CMOS technology. The measured current consumption is 61 mA from 1.8-V supply, and the active chip area is 0.5 Ã— 0.6 mm².

Keywords

CMOS integrated circuits; UHF amplifiers; UHF integrated circuits; comparators (circuits); current-mode logic; radio receivers; BER; CMOS technology; PAM receiver; bit rate 8 Gbit/s; current 61 mA; current consumption; current mode amplifier; current-mode logic circuit; frequency 2 GHz; high speed comparator; ten-level pulse-amplitude modulated encoded data signals; voltage 1.8 V; Area measurement; Bit error rate; CMOS logic circuits; CMOS technology; Frequency measurement; Logic circuits; Logic design; Pulse amplifiers; Pulse measurements; Pulse modulation; 10-PAM; CMOS; Receiver; Transceiver; Transmitter;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits, ISIC '09. Proceedings of the 2009 12th International Symposium on

Conference_Location

Singapore

Print_ISBN

978-9-8108-2468-6

Type

conf

Filename

5403721