A low dropout regulator for SoC with high power supply rejection and low quiescent current

A CMOS low dropout regulator (LDR) with high power supply rejection (PSR) and without large output capacitor is proposed for system-on-chip (SoC) power management applications. By cascoding a power NMOS with the PMOS pass transistor, high PSR over a wide frequency range is achieved. The gate drive of the cascode NMOS is controlled by an auxiliary LDR that draws only 1 ¿A from a small charge pump, leading to a very low quiescent current. A prototype LDR is fabricated using a standard 0.35 ¿m CMOS process, occupying an active area of 0.066 mm². The input is 1.6 V and the output is 1.2 V with a maximum load current of 10 mA. The measured worst-case PSR at full load without using large output capacitor is -22.7dB up to 60 MHz. The line and load regulations are 0.25 mV/V and 0.32 mV/mA respectively.