A PTL based highly testable structured ASIC design approach

In this paper, we describe a highly testable structured ASIC design methodology which utilizes a regular, prefabricated array of pass transistor logic based if-then-else (ITE) cells as the building block for the circuit. Given a logic netlist, we first construct reduced order binary decision diagrams (ROBDDs) for the circuit in a partitioned manner, thereby allowing the approach to handle large designs. Test generation for each of these partitions can be performed extremely efficiently. The design methodology has been demonstrated to implement sequential as well as combinational designs, with low area and delay overheads compared to an ASIC approach.