Efficient approximately-timed performance modeling for architectural exploration of MPSoCs

In this paper, we propose an efficient modeling approach that permits simulation-based performance evaluation of MPSoCs at electronic system level (ESL). The approach is based on a SystemC simulation framework and allows for evaluating timing effects from resource contention when mapping applications to MPSoC platforms. The abstraction level used for modeling timing corresponds to approximately-timed transaction level models. This allows for an accurate performance modeling, including temporal effects from preemptive processor scheduling and bus arbitration. However, in contrast to standard SystemC TLM, application mapping and platform models are configurable and, thus, enable design space exploration at ESL. We use a motion-JPEG decoder application to illustrate and assess the benefits of the proposed approach.