Exploration of embedded memories in SoCs using SystemC-based functional performance models

The quantitative exploration of the memory design space is needed early in the design process of deeply embedded systems. For predictive results, models are required that carefully consider three performance-impacting effects of memory accesses: synchronization, arbitration, and latency. Our approach combines functionally-correct performance simulation with memory models of different accuracy. Extending a SystemC-based framework, we leverage performance annotations to capture dynamic effects in the system. Indicative performance figures can be derived using only sparse synchronization and a statistical memory access distribution model. We observe a better predictability by 4X for our design compared to existing work. A case study demonstrates our approach exploring tradeoffs between local and shared memories in a multiprocessor SoCs using a wireless packet processing application.