EMI hardening of GPS clock — A case study

The GPS Clock comprises GPS Receiver and Time processing unit. The typical GPS clock generates 1 PPS and synchronizes to the 1 PPS from a GPS Receiver. Designing the GPS clock with the allowable drift of ± 500nseconds is highly sophisticated. The system´s control and synchronization mechanism, the locking mechanism used by phase lock loop (PLL) technique are some of the important critical parameters. These critical parameters are mostly susceptible to electromagnetic interference. The interconnecting cable lengths between modules will also add the EMI. Providing the low resistance discharge path to the electrostatic currents is most essential to achieve the EMC. Altering of equipotencial surface will degrade the performance of the components mounted on the chassis. Controlling EMI in a system which operates on AC & DC voltages. In this paper the authors brought out the failures against EMI, the detailed step by step analysis carried out on problems faced during EMI/EMC performance evaluation and the EMC measures taken to counter the EMI problems. After achieving the EMC, the EMI/EMC performance evaluation was also carried out on 5 more units to confirm the stability of EMC.