Recent Advances and Trends in SOI CMOS Technology

Fully depleted SOI CMOS technology is now showing decisive advantages (in contrast to incremental advantages) over bulk CMOS. Low-voltage (as low as 0.5 V), low-power (in the tens of nanowatts range) circuits operating at respectable speeds have been demonstrated. In the DRAM field, a three-fold reduction of the storage capacitor can be obtained, owing to the lower bit line capacitance, the lower access transistor leakage current and the higher soft-error immunity provided by SOI technology. High-temperature analog and digital circuits benefit from the reduced leakage current and the absence of leakage to the substrate found in SOI devices.