DocumentCode
513670
Title
A 0.6 μm Si Bipolar Technology with 17 ps CML Gate Delay and 30 GHz Static Frequency Divider
Author
Bock, J. ; Popp, J. ; Felder, A. ; Meister, T.F. ; Rest, M. ; Schreiter, R. ; Aufinger, K. ; Kopl, R. ; Boguth, S. ; Treitinger, L.
Author_Institution
Siemens AG, Corporate Research and Development, Microelectronics, Munich, Germany
fYear
1995
fDate
25-27 Sept. 1995
Firstpage
417
Lastpage
420
Abstract
A CMOS compatible 0.6 micron silicon bipolar technology with 34 GHz cut-off frequency for mixed digital/analogue applications is presented. CML gate delay of 17 ps, static divider operation of up to 30 GHz and minimum noise figure of 0.8 dB at 2 GHz confirm the wide range of potential circuit applications.
Keywords
CMOS analog integrated circuits; CMOS digital integrated circuits; CMOS process; CMOS technology; Cutoff frequency; Delay effects; Frequency conversion; Noise figure; Production; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1995. ESSDERC '95. Proceedings of the 25th European
Conference_Location
The Hague, The Netherlands
Print_ISBN
286332182X
Type
conf
Filename
5435919
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