Shallow Trench Isolation for High Density Flash Memories

We combine a LArge Tilt Implanted-Sloped Trench Lsolation(LATI-STI) for NMOS and Diffusion Doped Trench Sidewalls for PMOS devices to achieve 0.70¿m pitch isolation. High performance periphery devices and high endurance Flash Memories cells of the 64Mbit generation and beyond are obtained. The trench refill oxide thickness uniformity and dishing after Chemical Mechanical Polishing(CMP) are optimized by a correct die mapping, a high mask filling factor and a non critical Qrcide Grooves(O.G.) etching step. 7 nm thin gate oxide QBD is optimized by minimizing thermal budget and stress at the trench upper corner. The active devices subthreshold and narrow channel characteristics are correlated by using the differential body effect method. Subthreshold hump suppression under large body bias requires 70° sloped trenches combined with a 50° tilted Boron sidewall implant on NMOS and a diffused N-Well for PMOS. 0.40¿m finished N, P metal gate field devices demonstrate higher than 15V isolation.