Advanced Architectures for 0.18-0.12μm CMOS Generations

This paper attempts to answer the question of why we should deviate from the scaling theory by accepting some new device architectures, and the reason for this, within the frame of 0.18-0.12μm generations. Next we analyze theoretically and experimentally the advantages and disadvantages of a certain number of advanced device architectures such as: GP (ground plane), heterostructures, mid-gap gate etc. Implementation of these concepts within the CMOS process is discussed. Concerning the technological development of these architectures, GRESSI experiments with 0.18μm gate length (drawn) MOSFETs are reported and analyzed with respect to such technologies as : (i) - heavy ion implantation leading to RCP (retrograde channel profiles, a first order approximation of GP), (ii)) - heavy ion implants followed by intrinsic Si epitaxy, approaching more closely an ideal PSD (pulse shape doping) and therefore taking better advantage of the GP principle, (iii) - strained Si channels, (iv) - SiGe epi channels with 15% and 30% Gefraction, (v) - poly SiGe gate. All these architectures are compared with reference to conventional B/Ph implanted devices. Conclusions are drawn for the future device architecture orientations.