• DocumentCode
    515831
  • Title

    56Gs/s ADC : Enabling 100GbE

  • Author

    Dedic, Ian

  • Author_Institution
    Fujitsu Microelectron. Eur. GmbH, Maidenhead, UK
  • fYear
    2010
  • fDate
    21-25 March 2010
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    A 100 G coherent receiver needs 4 56 Gs/s ADCs and a tera-OPs DSP which dissipate only tens of watts. This paper discusses the forces pushing towards a single-chip CMOS solution, and the challenges in realising this.
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; optical receivers; quadrature phase shift keying; ADC; DP-QPSK; dual-polarisation quadrature phase-shift keying; optical transport network; single-chip CMOS solution; CMOS technology; Costs; Digital signal processing; Digital signal processing chips; Energy consumption; Optical fiber networks; Optical modulation; Optical network units; Optical receivers; Prototypes;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Optical Fiber Communication (OFC), collocated National Fiber Optic Engineers Conference, 2010 Conference on (OFC/NFOEC)
  • Conference_Location
    San Diego, CA
  • Electronic_ISBN
    978-1-55752-884-1
  • Type

    conf

  • Filename
    5465542
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=515831