A Fully Testable Single-Chip 32-Bits Multi-formats Floating Point Processor

Author

Bornes, P. ; Derieux, A. ; François, J.A. ; Manga, C. ; Mehrez, H. ; Noguez, C. ; Shamsa, K.

Author_Institution

Service d´´Electron., Centre de Bruyeres-Le-Chatel, Bruyeres-Le-Chatel, France

Volume

1

fYear

1990

fDate

19-21 Sept. 1990

Firstpage

273

Lastpage

276

Abstract

This article describes the architecture and design of a fully testable floating point processor. It performs 32-bits floating point arithmetic operations (addition, subtraction and multiplication) and it also performs integer-to-floating point, floating point-to-integer and inter-format conversions using either IEEE- P745 10.0, DEC-VAX or a two´s complement format To enhance performances, the processor includes a 16×32 bits double access RAM. Designed for CMOS hard technologies, the chip contains about 55000 transistors in 90 mm2 and performs a hole operation in less than 200 ns.

Keywords

floating point arithmetic; CMOS hard technology; addition; double access RAM; floating point arithmetic operation; floating point-to-integer conversion; integer-to-floating point; inter-format conversion; multiplication; subtraction; testable single-chip multiformats floating point processor; Adders; CMOS technology; Engines; Floating-point arithmetic; Multiplexing; Random access memory; Read-write memory; Software performance; Testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1990. ESSCIRC '90. Sixteenth European

Conference_Location

Grenoble

Print_ISBN

2-86332-087-4

Type

conf

Filename

5467790