Design and Comparison of Gaas and CMOS Redundant Divider

This paper presents a combinatorial circuit for fast division Q := A+D. High speed is achieved thanks first to an improved algorithm and second to its realization in Gallium Arsenide. An n bit divider produces an n bit quotient Q in 9*n NOR-gate-delays with n² add/subtract cells (called tail) controlled by n controllers (called head). The implementation of the divider circuit has been achieved by using buffering technique and full custom layout methodology that are well suited for high performance designs in GaAs direct-coupled FET Logic (DCFL). Comparison of GaAs and CMOS implementation are given.