DocumentCode
516472
Title
Voltage Reduction for 4Mbit-CMOS-DRAM
Author
Eichfeld, H. ; Rieger, J. ; Harter, Jonathan
Author_Institution
Siemens AG, Corporate Research and Development, Otto Hahn Ring 6, D-8000 Munich 83, FRG; Lehrstuhl f?r Technische Elektronik, Universit?t Erlangen, Kauerstr. 9, D-8520 Erlangen, FRG
fYear
1986
fDate
16-18 Sept. 1986
Firstpage
7
Lastpage
9
Abstract
Different types of voltage reduction circuits for application to VLSI-DRAMs have been investigated. A lumped element network description of the circuits and the distributed power supply of a 4Mbit chip has been developed to model the load characteristic of the memory in a realistic way. It is shown, that the peak currents in the active cycle can be delivered by the distributed capacities of the supply lines, thus the switching speed of the reduction circuit can be substantially less than the switching speed of the decoder or amplifier circuits.
Keywords
Capacitance; Circuit simulation; Decoding; Load modeling; MOSFETs; Power supplies; Random access memory; Switching circuits; Threshold voltage; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1986. ESSCIRC '86. Twelfth European
Conference_Location
Delft, The Netherlands
Type
conf
Filename
5468238
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