• DocumentCode
    516496
  • Title

    A Highly Flexible 60K-Gates CMOS Master Image

  • Author

    Schettler, H. ; Koetzle, G. ; Schulz, U. ; Wagner, O.

  • Author_Institution
    IBM Laboratories, Boeblingen, Germany
  • fYear
    1986
  • fDate
    16-18 Sept. 1986
  • Firstpage
    50
  • Lastpage
    52
  • Abstract
    A 1.0 ¿m CMOS technology with 3 layers of metal is used to implement a high density Master Image that contains LOGIC and RAMs. The Image allows the usage of even more than 1,000,000 transistors. A hierarchical design methodology is described. This chip offers variable sized physical partitions and RAM macros. No fixed area sizes and locations for partitions and macros are necessary. Chip density and performance of oustomized chips are approached by the described methodology at significantly lower development cost and development time.
  • Keywords
    Automatic logic units; CMOS logic circuits; CMOS technology; Design methodology; Integrated circuit interconnections; Logic design; Logic gates; Power distribution; Wire; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1986. ESSCIRC '86. Twelfth European
  • Conference_Location
    Delft, The Netherlands
  • Type

    conf

  • Filename
    5468280
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=516496