• DocumentCode
    516504
  • Title

    A Fast 16 Ã\x97 16 Bit Asynchronous CMOS Multiplier

  • Author

    Kamp, W. ; Knauer, K. ; Lackerschmid, E.

  • Author_Institution
    Corporate Research and Development, Siemens AG, Otto-Hahn-Ring 6, D-8000 Mÿnchen 83, W. Germany
  • fYear
    1986
  • fDate
    16-18 Sept. 1986
  • Firstpage
    59
  • Lastpage
    61
  • Abstract
    We present a very fast CMOS multiplier for two 16 bit numbers. This multiplier uses special architecture and circuitry techniques - like Booth algorithm, Wallace tree algorithm and Carry Select Adder - to reduce both circuit area and delay time.
  • Keywords
    Adders; Circuits; Clocks; Decoding; Delay effects; Encoding; Equations; Hardware; Research and development; Signal processing algorithms;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1986. ESSCIRC '86. Twelfth European
  • Conference_Location
    Delft, The Netherlands
  • Type

    conf

  • Filename
    5468289
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=516504