An Asynchronous 16*16 Pixel Array-Processor for Morphological Filtering of Greyscale Images

We present a fine-grain asynchronous 16*16 VLSI array processor. It demonstrates how asynchronism can be exploited both at functional and architectural levels. Our design flow is based on a standard cells approach that combines Differential Cascode Voltage Switch Logic blocks and standard CMOS gates. The chip has been fabricated using the CNET/SGS-Thomson 0.5 ¿m CMOS triple metal layer technology. It includes 800 000 transistors in an area of 8*9 mm². It allows real-time iterative morphological filtering of greyscale 256*256 pixels images at a 30 Hz frame rate using a single chip.