Complex 3D-CMOS Circuits based on a Triple-Decker Cell

We present circuit design concepts for a vertically integrated process. This process with its three stacked transistor channels leads to the very efficient basic circuits: Inverter, Selector and NAND2. These elements are used to build a cell library with standard elements like NOR, Latches, Flip-flops etc. Special macro-blocks as Multiplier, SRAM, CAM complete the circuit library. Area requirements for static CMOS logic ranges from 50% down to 25% compared to two-dimensional CMOS. These figures include the wiring and are caused by the transistor stacking and the large number of interconnection layers used in the three-dimensional CMOS process.