Accuracy-Controlled VLSI Arrays for Signal Processing

The DIGILOG leading `1´-first, recursive multiplication algorithm and its efficient mapping onto a VLSI architecture is presented. Multiplication accuracy is studied and the accuracy control method is discussed. Due to low chip area requirements, DIGILOG exhibits a good area/time product that supports highly parallel operation of many small computational elements on a chip; it permits a trade-off of computational accuracy versus throughput. A prototype chip is presented that contains nine reconfigurable DIGILOG elements on a CMOS 1.2¿m 2nd generation sea-of-gates GATE FOREST. Depending on the selected accuracy, the chip achieves a maximum operation rate of up to 360 million 8-bit multiplications per second. The chip can be configured to perform filtering operations ranging from one-dimensional FIR-filtering to low-level image processing algorithms.