A 100 MHz highly accurate CMOS zero-phase detector for timing recovery systems

A phase detector for timing recovery phase locked loops with an accuracy better than 0.5 % for input frequencies up to 100 MHz is presented. The core of the phase detector consists of two modified Gilbert cells combined so that the offset in their output current is cancelled. This core is expanded with logic circuitry at the input to make the phase detector suitable for timing recovery applications. The switching speed of the input logic does not directly affect the accuracy of the phase detector. The design is realised in a 0.7¿ CMOS process. Symmetry and shielding techniques are used in the layout to increase the circuits performance at high input frequencies.