Multi-bank memory access scheduler and scalability

With the progress of semiconductor manufacture techniques and the development of processor architecture, the gap between processor and DRAM speed is becoming larger and larger, memory bandwidth is now the primary bottleneck of improving computer system performance. Modern DRAM provide several independent memory banks, according to this character, we present a virtual channel based memory access scheduler, and least wait time and read-fist schedule approach. This approach significantly reduce observed main memory access latency and improve the effective memory bandwidth.