Implementation of a high performance subword parallelism 64-Bit IMAC for multimedia service

Multimedia applications inherently involve large amounts of data-level parallelism. This paper proposes the architecture of a 64-bit integer multiply accumulator (IMAC), which supports subword parallelism and extends signed and unsigned integer operations. With pipeline technology, its VLSI design and implementation has been completed by using UMC 0.18μm standard CMOS process. Compared with conventional IMAC for general purpose computation, it can perform one 64×64+64, two 32×32+32, four 16×16+16 bit, or eight 8×8+8 bit multiply accumulation operation in one single cycle respectively, while requiring only a little more area and delay. The proposed architecture enhances the performance of IMAC for multimedia applications.