An expected-utility based approach to variation aware VLSI optimization under scarce information

In this research, we propose a novel approach for simultaneous optimization of power, crosstalk noise and delay via gate sizing, in the presence of scarce information about the distribution of the variations. The methodology uses the concepts of utility theory and risk minimization to identify a deterministic equivalent model of the stochastic problem, ensuring high levels of expected utilities of constraints, and significant speedup in the optimization process for large circuits. A comparative study with an existing gate sizing methodology shows that our method is multi-fold faster as well as comparable in terms of the optimization.