DocumentCode
524806
Title
Minimum buffer insertions for clock period minimization
Author
Huang, Shih-Hsu ; Jhuo, Guan-Yu ; Huang, Wei-Lun
Author_Institution
Dept. of Electron. Eng., Chung Yuan Christian Univ., Chungli, Taiwan
Volume
1
fYear
2010
fDate
5-7 May 2010
Firstpage
426
Lastpage
429
Abstract
It is well known that the combination of clock skew scheduling and delay insertion can achieve the lower bound of sequential timing optimization. Previous approaches focus on the minimization of required inserted delay. However, from the viewpoint of design closure, minimizing the number of inserted buffers is also very important. In this paper, we propose a linear program to minimize the number of inserted buffers under the constraint on the lower bound of required inserted delay. Note that our approach guarantees obtaining the optimal solution. Experimental data consistently show that our approach can greatly reduce the number of inserted buffers.
Keywords
clocks; integrated circuit design; logic design; minimisation; scheduling; sequential circuits; timing; buffer insertions; clock period minimization; clock skew scheduling; delay insertion; design closure; linear program; sequential timing optimization; Automatic control; Clocks; Communication system control; Constraint optimization; Delay effects; Minimization; Pulse circuits; Registers; Sequential circuits; Timing; High performance; Sequential circuits; Timing optimization;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Communication Control and Automation (3CA), 2010 International Symposium on
Conference_Location
Tainan
Print_ISBN
978-1-4244-5565-2
Type
conf
DOI
10.1109/3CA.2010.5533776
Filename
5533776
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