Low Vgs P-ch LDMOS with Sallow Pwell from 8V to 60V

We present a new 0.3 5um BCD technology with a capability of 8 to 60V p-ch LDMOS. The proposed p-ch LDMOS employs the S-PWELL in the p-epi region to ensure high breakdown voltage and low on-resistance. The Rsp of the proposed 60V p-ch LDMOS is lower by 42% than conventional one. And we modified the 300Å gate oxide of the original p-ch LDMOS to 125Å so that the proposed p-ch LDMOS is efficient for applications which 5V is applied to Vgs. Those results can reduce chip size significantly. The process has no thermal budget modification but simply move implant step so that no extra mask is needed. Also it is compatible with the conventional BCDMOS and has competitive performance compared to 0.15-0.25um BCDMOS of other competitors.