FPGA-based cryptosystem with combined stream-block cipher and digital chaos generator

This paper presents results of studies on the implementation of integrated cryptographic system combining an initial stream ciphering with block ciphering based on the AES algorithm. A novel architecture of fast, single-chip cryptosystem using pipelined AES engines combined with the initial stream cipher based on the digital chaos generator is proposed. The throughput of the system implemented in the Virtex 5 FPGA equals to 17.07 Mbps, and is much better than reported so far for the other low-cost, 8-bit FPGA-based architectures. This cryptosystem can be used in mobile electronic equipment for secure, real-time transmission of digital signals, including audio-video applications.