Ultra low loss and high linearity SPMT antenna switch using SOI CMOS process

Low loss and high linearity antenna switch is designed and implemented using 0.18 μm silicon-on-insulator(SOI) CMOS process for GSM/WCDMA mobile phone front-ends. Body-contacts(BC) NFETs from partially depleted (PD) SOI were chosen to implement low loss and high power antenna switch. The antenna switch employs a conventional multi-stacking FET structure to distribute voltage stress toward each FETs. Measurement results demonstrate less than 0.5 dB insertion loss up to 2 GHz and 80 dBc harmonics at all bands in the case of a single pole four throw(SP4T) switch design. This SP4T switch integrates controller to be used in the Tx module for GPRS/EDGE application. The controller operates from 3 V to 4.5 V. The design of antenna switches using multi-stack FETs can be extended by SP10T switch design with exceptional low loss and high linearity.