Parameterized bus interface design based on Verilog language

With the rapid development of the designing technology and manufacturing technology about deep submicron of the integrated circuit, SoC (System-on-a-Chip) technology has become the mainstream of integrated circuit design in 21st century, and become current development trend of very large scale integrated circuits. At present, the design of SoC usually adopts the Hierarchization architecture on chip bus, bus interface is the interface of system bus and peripheral bus, and all peripheral IP cores in the SoC go on data communication with processor through interface. For improve the reusability of IP cores, we should improve the configurability of bus interface as much as possible, the parameterized design is a common solution to realize the configurable. This paper studies the design of a parameterized bus interface, and quantitative analysis the parameterized design how effects on IP´s reusability compared with nonparameterized design, using LOC (line of code) as a metric.