DocumentCode
533357
Title
On-chip ESD protection with improved high holding current SCR (HHISCR) achieving IEC 8kV contact system level
Author
Bart, Sorgeloos ; Ilse, Backers ; Olivier, Marichal ; Bart, Keppens
Author_Institution
Sofics (formerly known as Sarnoff Eur.), Gistel, Belgium
fYear
2010
fDate
3-8 Oct. 2010
Firstpage
1
Lastpage
10
Abstract
For the design of on-chip ESD clamps against system level ESD stress three main challenges exist: reach a high failure current, ensure latch-up immunity and limit transient overshoots. Bearing these in mind, high system level ESD requirements should be within reach. A novel improved high holding current SCR is introduced fulfilling all three requirements within drastically reduced silicon area.
Keywords
IEC standards; electrostatic discharge; failure analysis; thyristors; transient analysis; HHISCR; IEC contact system level; high failure current; high holding current SCR; on-chip ESD clamp design; on-chip ESD protection; system level ESD stress; transient overshoots; voltage 8 kV; Anodes; Clamps; Electrostatic discharge; Resistors; System-on-a-chip; Thyristors; Voltage measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Overstress/ Electrostatic Discharge Symposium (EOS/ESD), 2010 32nd
Conference_Location
Reno, NV
Print_ISBN
978-1-58537-182-2
Electronic_ISBN
978-1-58537-182-2
Type
conf
Filename
5623725
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