DocumentCode
534208
Title
A SRAM-Based FTL Design in Solid State Drives Using Block Associative Mechanism
Author
Bo, Li ; Changsheng, Xie ; Chen, Lu ; Fen, Wang
Author_Institution
Dept. of Comput., Huazhong Univ. of Sci. & Technol., Wuhan, China
Volume
2
fYear
2010
fDate
16-18 July 2010
Firstpage
104
Lastpage
109
Abstract
When Solid state drives began to enter our life and gradually became the mainstream device in the storage industry. Some issues incur the people attention in pursuit of optimal performance. This paper proposed an on-chip SRAM-based FTL design to improve the efficiency of the SSD random write and reduce the amount of erasure operations. By simulation experiments of SSDsim, we demonstrated the efficiency of our design. At the end of this paper, I gave our future directions in this work.
Keywords
SRAM chips; flash memories; SSDsim; block associative mechanism; flash translation layer design; on-chip SRAM; solid state drives; storage industry; Computer architecture; Drives; File systems; Layout; Optimization; Random access memory; Solids; FTL; Lifetime; Solid state drives; mapping mechanism;
fLanguage
English
Publisher
ieee
Conference_Titel
Information Technology and Applications (IFITA), 2010 International Forum on
Conference_Location
Kunming
Print_ISBN
978-1-4244-7621-3
Electronic_ISBN
978-1-4244-7622-0
Type
conf
DOI
10.1109/IFITA.2010.349
Filename
5634901
Link To Document