Eliminating stress-induced junction leakages at minimum polysilicon-active space in advanced embedded high voltage CMOS technologies

The mechanism leading to a significant leakage bin fallout, resulted from a slight (0.05um) active-polysilicon space reduction was discussed. Effective solutions involving redesigning the polysilicon track or using an alternative process architecture were presented. A robust DfM guideline applicable to conventional MOS as well as high voltage extended-drain MOS (with an embedded shallow trench isolation structure in the drain region) architectures was also presented.