Pipelined on-chip bus architecture with distributed self-timed control

This paper describes an on-chip bus architecture targeted for the globally asynchronous locally synchronous system-on-chip design strategy. The proposed pipelined bus structure is composed of asynchronously interacting segments which can operate in parallel. The bus is segmented using transfer stages which partition bus into a set of point-to-point interconnects. Self-timed arbitration and control is distributed among the pipelined stages to enable parallel operation of distinct segments, to prevent problems present in a globally clocked system, and to increase design modularity. In a 0.18 μm technology, each bus segment is capable of transferring data at a maximum throughput of 1.2 giga data items per second concurrently in both directions.